An Energy Conscious Topology Augmentation Methodology for On-Chip Interconnection Networks

Abstract

On-chip communication modular scalable packet-switched micro-network of interconnects generally known as Network-on-Chip NoC architecture can be designed as regular or application-specific irregular network topologies Application specific custom network topologies are advantageous in terms of optimized design according to given performance metrics and regular network topologies are advantageous in terms of its modularity lower design time and efforts required and thus are suitable for mass production So to offer the advantages of both the topologies this paper proposes a methodology to augment the regular topology according to the application characteristics The experimental results demonstrate that the proposed methodology can reduce dynamic communication energy consumption by on average of 32 79 and reduction in average per flit latency by on average of 16 22 over regular 2D NoC architecture